EE6312: Project FAQ

Here I will post answers to commonly asked questions.

1. How big should the sampling capacitor be?
• The sampling capacitor determines how much noise is present in the sampling circuit, regardless of the value of the switch resistance.  This phenomenon is commonly called kT/C noise, and is elaborated upon in all the references given.  For this project, once you have your Vfs and Vlsb values, you should size the sampling capacitor such that the rms kT/C noise is at least 4x smaller than Vlsb.
2. How does a pipelined ADC work?
• Here are two examples of short pipelined ADCs to give the idea. The examples given assume a single-ended Vfs of 1V, and 4b resolution. My input voltage is 0.7V.  The output code should be 1011=0.6875V, because the next higher output code is 1100=0.750V. The stage to stage behavior is then:
• Vin1 = 0.7V > 0.5V so BIT3 = 1, Res1 = 2(0.7V - 0.5V) = 0.4V
• Vin2 = 0.4V < 0.5V so BIT2 = 0, Res2 = 2(0.4V -   0V) = 0.8V
• Vin3 = 0.8V > 0.5V so BIT1 = 1, Res3 = 2(0.8V - 0.5V) = 0.6V
• Vin4 = 0.6V > 0.5V so BIT0 = 1, Res4 = 2(0.6V - 0.5V) = 0.2V.
• As a sanity check, you make sure the residue is correct: 0.2V residue after 4 stages is 0.2V/16=0.0125V referred back to the input, and indeed 0.7V-0.6875V=0.0125V.
• Just as another example, what if we do two stages, but resolve two bits per stage.  Then the sub-ADC voltages are 00=0V, 01=0.25V, 10=0.5V, and 11=0.75V. Our output code should be the same as before.
• Vin1 = 0.7V > 0.50V so BIT32 = 10, Res1 = 4(0.7V - 0.50V) = 0.8V
• Vin2 = 0.8V > 0.75V so BIT10 = 11, Res2 = 4(0.8V - 0.75V) = 0.2V
• Once again, the output code is 1011, and the residue after 2 stages (equivalent to the residue after 4 stages of the 1-bit per stage case) is 0.2V.
3. How are Vfs and Vref related? How should we choose Vfs?
• Vfs is the full-scale input range.  So, suppose I have a Vdd=1.2V.  I'm going to use a two-stage op-amp, so the output stage swing is limited to a Vdsat above and below.  Therefore, it's reasonable to assume my op-amp will operate from 0.3V to 0.9V.  My common mode voltage is 0.6V, and my Vfs is 0.6V. (0.3V-0.9V)  Thus. if I put in 0.3V (minimum) into the converter, I should get 000000... from the output, if I put in 0.9V (maximum) I get 1111111... and if I put in 0.6V (differential 0) I should get 011111... Of course, the encoding scheme is unimportant.
• Vref on the other hand is the sub-ADC output voltage. Basically, if you resolve that the input to the stage is above a certain threshold, you have to then subtract that value before passing the residue on to the next stage.  To visualize this, draw the MDAC transfer function plotting Vout vs. Vin.  It should look like a sawtooth wave.
4. My op-amp model doesn't look like it works.
• So far, I haven't found any major problems in the op-amp models. The problems I've found are:
• The single-ended model has Adiff a factor of pi off from what it should be.
• Both models suffer a common-mode offset, which is unimportant in practice when wrapped in feedback, but may appear strange when operated open-loop.  The common mode output should be calculated by: Vout,cm = (Vin,cm - Vcm)*Acm + Vcm.  Instead, it's currently calculated as: Vout,cm = Vin,cm*Acm + Vcm.  Please feel free to modify the sub-circuit if this bothers you.
• So far, people experiencing strange looking results should instead make sure they're expecting the right thing.  For example, if I have an op-amp with 1GHz GBW and a Adiff of 1000, then the first pole is at 1MHz.  Thus, if I pass in a 1Vp-p 1KHz sine wave, I should see that sine wave 1000Vp-p at the output, right? Well, it depends on the amplitude of the input sine wave. The wave as such has a maximum slew rate (derivative at every 1ms) of 2*pi*f*Adiff=6V/us.  If your slew rate is smaller than this, your output will be slew rate limited.
• The other issue, with seemingly time-varying gain, is the fact that the common-mode response has different dynamics than the differential response.  Instead of separately plotting Vout_p and Vout_n and looking at how strange it is, to understand the differential response you HAVE to look at (Vout_p-Vout_n).  Similarly, to see the common mode response, you have to look at (Vout_p+Vout_n)/2.
• Please remember to be reasonable with the op-amps; the models try to mimic some realistic behaviors, but a real transistor-based op-amp will be even more non-ideal.  Open loop responses are difficult to measure without some thoughtful test circuits.
• The top resistor in the output stage of the one-stage model is missing a factor of 2; the correct expression in the resistance should be pPar("Adif")/(2*3.1416*pPar("GBW")*pPar("CL"))/2. Alternatively, you can copy and paste the lower resistor in place of the upper.
5. Transmission Gate Sizing.
• I notice many of you want to size the transmission gates to linearize resistance across the input range.  While this is a valid concern, since we don't have a spec on the linearity of the ADC, you should actually size the N and P switches equal, so that you minimize charge injection.
6. Input parasitic Capacitance
• Remember that if your sampling capacitance is too small, the loop gain of the SHA will be degraded significantly by the input capacitance of the amplifier.  This will lead to poor DC settling accuracy, as well as extending settling time.  Remember to account for this effect and over-design your op-amp somewhat.
7. Common Mode voltage
• Nothing says you need to choose a common mode voltage at Vdd/2, it just usually works out that way.  If the topology you choose works better with a common mode away from Vdd/2, go ahead and use it.
8. Load Capacitance
• The load seen by the op-amp is not just Cs, or 2Cs, but 3Cs (which holds true for any op-amp with reasonable gain). This is because the subsequent stage, in sample mode, has two Cs's tied together, and the current stage in hold configuration has a Cs in feedback tied to a virtual ground.  So be sure to account for this.
9. How do I create a reference current/voltage?
• You are allowed to use one ideal current source, with one node tied to either Vdd or Gnd.  From this current source you must generate all the voltage and current biases in your op-amp.  Your clocks are not included in this restriction, you can use ideal voltage sources for this.
10. How do I do PSS/PAC Analysis with Spectre?
    Some of you want to use switched capacitor common mode feedback circuits, which is a great idea.  However, the standard AC analysis doesn't understand that this is a sampled data system. To do the analogous AC analysis of a switched capacitor circuit, you need PSS and PAC analyses.
• PSS: Periodic Steady State.  When you do a PSS, you first have to remove or zero all periodic sources in your system except your clock.  Well, you don't, but it makes it easier.  In the list of fundamental tones, you should see your two (or however many) clock sources.  The important thing is, the value of the fequency should be equal to your clock frequency. Click "Beat Frequency" and specify the clock frequency. For "Number of Harmonics" put "0", and "Accuracy Defaults" choose "moderate".
• PAC: Periodic AC. Just as with an AC analysis, where you specify the AC source by setting the "AC Magnitude" of a particular source to be non-zero, you need to specify which AC source(s) will be used in the PAC by setting the parameter "PAC magnitude". If you set multiple sources to be non-zero, then the result will be a superposition of everything.  The rest of the PAC analysis is setup the same as an AC analysis.  Verify that the Beat Frequency is showing up as you entered in PSS, then specify the start-stop, sweep type, and number of steps.  Since you are not analyzing distortion, set the "Maximum Sideband" to "0" as with the PSS.
• In order to make sure you're only seeing the held value at the output (since during the sample phase the opamp output returns to near zero) you need to sample-hold the outputs.  To do this, I have provided a simple circuit level model of a sample and hold.  It is nearly ideal.  It is better to use two SH blocks, one for each Out+ and Out-.  Attach Nin and Nout to ground, and load Pout with a 1K resistor (or something similar) to ground, and attach the signal of interest to Pin.  The current through this resistor won't count toward your power spec, it's not drawn from Vdd. These are the parameters:
• Period: Set the period of your clock.
• Delay: add a half period delay depending on if you want the sample to capture phase 1 or phase 2.
• Aperture: leave blank, it sets the non-ideality for the sample time window.
• Bandwidth: this models a rise time for the output, leave blank.
• Sample and Hold
11. My Opamp has XXdB of AC gain, but I still see settling error for a full-scale transient input that suggests a much lower DC gain. Howcome?
• Remember, the AC analysis is the small-signal linearization around a particular point, and ignores an amplitude dependent effects.  In particular, gm and ro of a MOSFET are highly dependent on the value of Vds.
• Suppose your opamp has an AC gain of 60dB, and you propose a Vfs of -0.5V to 0.5V, which is a Vfs of 2V.  This means, if you have a transient input amplitude of 1V/1000=1mV differential, your open loop transient output should be 1V differential. So run a transient analysis with a sin wave input source, at sufficiently low frequency to be within the first pole bandwidth, and verify that your output is indeed what it should be. Most likely, your output will look heavily distorted ("camel humping") and not as large as you would like.
• Solution: re-evaluate the biasing of your output stage.  You may have to reduce your Vfs so that the output transistors have more headroom.
• Run a DC sweep to evaluate the output resistance of your output stage as a function of the differential output voltage.  Most likely you will see it very large for small differential outputs, and quickly degrade as the Vds of the output transistors decrease.
12. How do I measure the total power consumed by my opamp?
• In the calculator, run the opamp in a transient simulation, and measure the average current from your Vdd source, and multiply this value by your Vdd to get average power.  Your average power includes all your bias circuitry.
13. My circuit meets settling for DC and slow inputs, but not the full scale, highest frequency input, and I have GBW to spare.  Why is this?
• There could be two answers.  First, check that your common mode voltage is properly set by the CMFB circuit, and everything is operating in the right region.  Next, zoom into a settling step and calculate the actual time constant of the settling (measure the time it takes the output to get 1/e (where e=2.7) the way to the final value, and verify that this is a healthy fraction of your predicted GBW.
• If this checks out, look at your AC transfer function.  Do you see pole/zero doublets within the loop bandwidth?
• Finally, make sure that your switches are sized appropriately, in that at the end of the sample phase the value sampled onto the two capacitors is actually accurate enough.  There's nothing the op-amp can do in the hold phase if the sampled value of Vin is wrong to begin with.  You may have to re-simulate the bandwidth of your switches.
14. How do I verify the design at the system level?
• Here is a test circuit to show how to use the sample and hold block.  It also includes two other cells: ct_transfer and sub_dac. (which should actually be called sub_adc, but whatever)
• ct_transfer: this block computes the ideal transfer function of the full switched capacitor circuit.  All you need to set is vref.
• sub_dac: this is the ideal control for the "B" signals seen in the handout diagram, and it also includes switches.  Run the simulation in the top level "sc_top" to see how this all works.
• This might not be of any use to you, but it shows you how to use the sample and holds to obtain clean output plots.
• final_project