Journal Publications
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D. Pepe, I. Chlis , and D. Zito, " Transformer-based input integrated matching in cascode amplifiers: Analytical proofs ," IEEE Transactions on Circuits and Systems I, 2017.
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D. Pepe, I. Chlis, and D. Zito, "50 GHz active-LC CMOS oscillator: Theoretical study and experimental proofs," Radio Science, 2017.
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I. Chlis, D. Pepe, and D. Zito, "Transformer-coupled pi-network differential CMOS oscillator circuit topology," International Journal of Circuit Theory and Applications, Wiley, 2016.
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D. Pepe, I. Chlis, and D. Zito, "67-GHz three-spiral transformer CMOS oscillator," International Journal of Circuit Theory and Applications, Wiley, 2016.
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I. Chlis, D. Pepe, and D. Zito, "Phase noise analysis in CMOS differential Armstrong oscillator topology," International Journal of Circuit Theory and Applications, Wiley, 2016.
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I. Chlis, D. Pepe, and D. Zito, "Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology," International Journal of Circuit Theory and Applications, Wiley, vol. 44, no. 3, May 2015.
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I. Chlis, D. Pepe, and D. Zito, "Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair," Journal of Circuits, Systems and Computers, vol. 24, no. 4, April 2015.
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| [8]
I. Chlis, D. Pepe, and D. Zito, "Comparative analyses of phase noise in 28 nm CMOS LC oscillator circuit topologies: Hartley, Colpitts, and Common-Source Cross-Coupled differential pair," Scientific World Journal, Hindawi, 2014.
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Conference Publications
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J. Hudner, D. Carey, R. Casey, K. Hearne, P. Wilson de Abreu Farias Neto , I. Chlis, M. Erett,
C. Poon, A. Laraba, H. Zhang, S.L. Chaitanya Ambatipudi, D. Mahashin, P. Upadhyaya, Y. Frans, and K. Chang "A 112Gb/s PAM4 wireline receiver using a 64-way time-interleaved SAR ADC in 16nm FinFET," VLSI Symposium, 2018.
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I. Chlis, D. Pepe, and D. Zito, "A novel differential Colpitts CMOS oscillator circuit topology," IEEE Proc. of Irish Signals and Systems Conference, 2016.
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I. Chlis, D. Pepe, and D. Zito, "60 GHz CMOS VCO with Transformer Coupling Network," IEEE Proc. of Irish Signals and Systems Conference, 2016.
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I. Chlis, D. Pepe, and D. Zito, "A novel differential Hartley CMOS oscillator circuit topology," IEEE Proc. of Irish Signals and Systems Conference, 2016.
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| [5]
D. Pepe, I. Chlis, and D. Zito, "Transformer-based input integrated matching in cascode amplifier: circuit analysis and comparison with inductive degeneration," IEEE Proc. of Irish Signals and Systems Conference, 2016.
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| [6]
I. Chlis, D. Pepe, and D. Zito, "Analyses of phase noise reduction techniques in CMOS Hartley oscillator topology at the mm-waves: Noise filter and optimum current density," IEEE Proc. of IEEE Mediterranean Microwave Symposium (MMS), 2015.
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| [7]
I. Chlis, D. Pepe, and D. Zito, "Analyses of phase noise reduction techniques in CMOS Colpitts oscillator topology at the mm-waves: Noise filter and optimum current density," IEEE Proc. of Ph.D. Research in Microelectronics and Electronics (PRIME), 2015.
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| [8]
I. Chlis, D. Pepe, and D. Zito, "Analyses of phase noise reduction techniques in CMOS Hartley oscillator topology at the mm-waves: Inductive degeneration and optimum current density," IEEE Proc. of Irish Signals and Systems Conference (ISSC), 2015.
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| [9]
I. Chlis, D. Pepe, and D. Zito, "Analyses of phase noise reduction techniques in CMOS Colpitts oscillator topology at the mm-waves: Inductive degeneration and optimum current density," IEEE Proc. of Irish Signals and Systems Conference (ISSC), 2015.
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| [10]
I. Chlis, D. Pepe, and D. Zito, "Comparison on phase noise in common-source cross-coupled pair and Armstrong differential topologies," IEEE Proc. of Irish Signals and Systems Conference (ISSC), 2014.
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| [11]
I. Chlis, D. Pepe, and D. Zito, "Comparative analyses of phase noise in differential oscillator topologies in 28 nm CMOS technology," IEEE Proc. of Ph.D. Research in Microelectronics and Electronics (PRIME), 2014.
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| [12]
I. Chlis, D. Pepe, and D. Zito, "Phase Noise comparative analysis of LC oscillators in 28-nm CMOS through the Impulse Sensitivity Function," IEEE Proc. of Ph.D. Research in Microelectronics and Electronics (PRIME), 2013.
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A. Dimakos, R. K. Sharma, M. Bucher, and I. Chlis, "Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion," IEEE Proc. of International Conference on Electronics, Circuits, and Systems (ICECS), 2012.
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I. Chlis, and M. Bucher, "PMOS drain-bulk connected loads for Subthreshold Source-Coupled Logic," IEEE Proc. of Mixed Design of Integrated Circuits and Systems (MIXDES) 2011.
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