ELEN E4321 - VLSI Circuits - Project

Designing an SRAM array at the 90 nm tech node

What's this?

On this page, you'll find information regarding Bhargav's VLSI project that he completed in the Fall of 2007.

Project Description

The goal was to create a 64x64 (= 4 kilobyte) array of 6-transistor SRAM cells, as well as circuitry necessary for reading, writing and precharging the circuit. Design choices made during the project include choosing between static and (various styles of) dynamic logic, as well as speed and testability considerations. The schematic was built in Cadence Virtuoso Schematic, tested in Cadence Analog Design (previously known as Analog Artist) employing Spectre (as the simulator) and laid out using 90nm IBM CMOS technology (obtained via a student Non-Disclosure Agreement through MOSIS) in Cadence Virtuoso Layout.

To maximize speed and minimize area, domino logic was used, and the maximum frequency attained for the dynamic address decoder (usually the critical bottleneck for the entire circuit) was around 14 GHz. The SRAM cell was a design supplied to the students (since SRAM has evolved tremendously over several generations since it's inception). Bhargav discovered that the SRAM could overlap with it's neighbors (due to the common ground, wordline, bitline, and VDD connections), and making an ultra-compact 4-cell enabled easy replication.

The circuit passed Design Rule Checking (DRC) as well as Layout Vs Schematic (LVS) in Cadence. John P. Uyemura's CMOS Logic Circuit Design (link to Amazon) proved a great boon in designing and deciding between various logic styles, as well as understanding the fundamental functioning of the SRAM read-write mechanism.

Report

The project report is available here (warning, 2.0 megabyte PDF). Hand calculations for calculated stage capacitances and sizing are not shown.

Acknowledgments

Bhargav would like to thank adjunct faculty Azeez Bhavnagarwala for proposing such a relevant and challenging project, as well as course TA Omar Ahmad for his technical assistance.