ELEN E6304 - Topics in VLSI circuits - Project

Designing a clock and power distribution mechanism for a high-speed 16-core Network on Chip

What's this?

On this page, you'll find information regarding Bhargav's digital VLSI circuits project that he completed in the Spring of 2008. This project was a team effort headed by Prof. Kenneth Shepard (EE) with involvement from Prof. Luca Carloni (CS) to design a high-bandwidth communication system between processor cores in a Network on Chip (NoC) configuration.

Project Description

Bhargav's goal in this project was to design a clock and power distribution mechanism that would reach all the cores on the chip. The clock distribution mechanism was an H-tree-driven grid, with the clock grid being shielded by the power grid. Since the tree and the grid would need to be iterated upon, it was decided that Cadence SKILL code would be used to generate them in Cadence Virtuoso Layout. The buffers in the tree were designed by hand, also using Cadence Virtuoso Layout, and verified against the schematic drawn in Cadence Virtuoso Schematic. The technology in play was 90nm IBM CMOS technology (obtained via a student Non-Disclosure Agreement through MOSIS).

Report

The project specification contains unpublished proprietary information, and details are not available online.

Acknowledgments

Bhargav would like to thank Prof. Shepard for utilizing a project-centric view, and keeping the group meetings similar to what would be expected in a professional technical design setting. He would also like to thank course TA Omar Ahmad for helping with solutions to technical issues.